1. Field of the Invention
The present invention relates to a semiconductor memory module, and particularly relates to improvements in a refresh control technique for a storage device using a plurality of dynamic semiconductor memories.
2. Description of the Prior Art
Generally, a semiconductor memory module is formed of a semiconductor chip (RAM chip) mounted thereon that includes a plurality of dynamic RAMs (each of which hereinbelow will be referred to as a xe2x80x9cDRAMxe2x80x9d). More specifically, in a configuration of the semiconductor memory module, signals such as a chip-selecting signal and a refresh command signal are generated and supplied to the individual DRAMs. The chip-selecting signal indicates which one of the DRAMs is selected to operate according to a high-order bit of an address signal supplied from a microprocessor.
The refresh command signal provides refresh timing according to control signals supplied from a microprocessor. The control signals include a chip enable signal CE, a read enable signal RE, a row-address strobe signal RAS, and a column-address strobe signal CAS. Each of the DRAMs has a refresh control function of determining a refresh mode according to the row-address strobe signal RAS and the column-address strobe signal CAS, driving a word line to a selected level and performing a refresh operation.
Ordinarily, a memory cell array in a DRAM chip is divided into a plurality of memory banks, and is configured to drive only a selected part of the memory banks to perform a read/write operation. However, in a refresh operation, all the banks are operated, and the peak current therefore is increased. Thus, a high peak current flows into the DRAM module in the refresh operation, and a Vdd/GND noise (power-supply noise) occurs to cause a malfunction in the module.
FIG. 10 shows a conventional example of an ordinary type of a registered DIMM provided with eight DDR SDRAMs to have a xc3x978-word-configuration. In the configuration shown in the figure, a register buffer and a PLL circuit for generating a base clock are mounted on the module which is formed of a one-bank configuration.
When an external control signal Ext./S, which is a chip-selecting signal, is input to the module, an internal control signal Int./S is output from the register buffer and is transferred to all the DRAMs. As a result, in response to a command defined by combination of external control signals Ext./RAS, Ext./CAS, and Ext./WE, all the chips SDRAM-1 to SDRAM-8 are simultaneously operated according to internal control signals Int./RAS, Int./CAS, and Int./WE.
The circuit configuration of the register buffer mounted on the above-described module is known in the art as shown in FIG. 11. In the configuration, according to various control signals /RESET, Int.CK, Int./CK, and Vref, input signals Input 0 to 13 are individually delayed via an inverter and a flip-flop circuit (F/F). Thereafter, output signals Output 0 to 13 are generated.
FIG. 12 shows a function table of the output signals in response to H/L levels of the various input signals /RESET, CK, /CK, and Inputs.
FIG. 13 shows operational timings in the conventional configuration shown in FIG. 10. The operational timings represent timings of operation performed such that a refresh command (Refresh) of /RAS, /CAS, and /WE is input, and thereafter, an activation (Act) command is input. As shown in FIG. 13, at time T1, an external refresh command (Ext./RAS, Ext./CAS, and Ext./WE) is received by the register buffer, and at time T2 after one cycle operation from T1, an internal refresh command of Int./RAS, Int./CAS, and Int./WE is simultaneously received by each of the eight DRAMs.
In FIG. 13, a delay time tpd represents a necessary time set by totaling a delay time caused within the register buffer and a wiring delay time caused in the field from the register-buffer output to the SDRAM input. The Act command activates the bank in the DRAM chip. After the external Act command is input at time T4, an internal Act command is simultaneously received by the eight SDRAM-1 to SDRAM-8 at time T5. As shown in the figure, since all the eight DRAMs simultaneously start refresh operations, a great peak current flows to be a problem.
The present invention is made to solve the above-described problems. Accordingly, an object of the present invention is to provide a semiconductor memory module in which execution timings of a refresh command are differentiated and distributed to inhibit a great peak current from flowing when a plurality of DRAMs simultaneously enter refresh modes. Thus, generation of Vdd/GND noise is inhibited, and stable operation can thereby be implemented.
Another object of the present invention is to provide a novel register buffer used in a semiconductor memory module implementing the above features.
To achieve the above objects, the present invention provides a semiconductor memory module which is provided with a plurality of DRAMs, and when an input command is detected as a refresh command according to external control signals externally input to a register buffer for command-execution, internal control signals for a partial number of the DRAMs preliminarily selected among the plurality of DRAMs are delayed. Thus, the refresh command is executed with a time difference, and the semiconductor memory module prevents the plurality of dynamic semiconductor memories from simultaneously entering refresh modes to cause a great peak current to flow.
According to a first aspect of the present invention, a semiconductor memory module is provided with a plurality of dynamic semiconductor memories, and generates internal control signals as a command to be applied to the plurality of individual dynamic semiconductor memories according to external control signals externally input to thereby execute the command. The semiconductor memory module includes: mode determining means for determining whether or not the command is a refresh command in a refresh mode according to the internal control signals; and delay means for establishing a delay in applying the internal control signals to a partial number of dynamic semiconductor memories preliminarily selected among the plurality of dynamic semiconductor memories. Thus, the refresh command is transferred to the plurality of dynamic semiconductor memories with a time difference according to the delay in the refresh mode.
By this configuration, since the plurality of dynamic semiconductor memories that simultaneously perform refresh operations on the module can be distributed to the plurality of groups, the peak current can be significantly reduced.
According to a second aspect of the present invention, there is provided a register buffer device used in a semiconductor memory module having a plurality of dynamic semiconductor memories mounted thereon, and the register buffer device includes: means for generating internal control signals for executing a command for the plurality of individual dynamic semiconductor memories according to external control signals externally input to the register buffer device. The register buffer device further includes mode determining means for determining whether or not the command is a refresh command in a refresh mode according to the external control signals; and delay means for establishing a delay in the internal control signals to be supplied to a partial number of dynamic semiconductor memories preliminarily selected among the plurality of dynamic semiconductor memories. Thus, the refresh command is transferred to the plurality of dynamic semiconductor memories with a time difference according to the delay in the refresh mode.
According to a third aspect of the present invention, there is provided a register buffer device used in a semiconductor memory module having a plurality of dynamic semiconductor memories mounted thereon. The register buffer device includes control means for performing control operations of: generating internal control signals for executing a command for the plurality of individual dynamic semiconductor memories according to external control signals externally input to the register buffer device; determining whether or not the command is a refresh command in a refresh mode according to the external control signals; and establishing a delay in the internal control signals to be supplied to a partial number of dynamic semiconductor memories preliminarily selected among the plurality of dynamic semiconductor memories. Thus, the refresh command is transferred to the plurality of dynamic semiconductor memories with a time difference according to the delay in the refresh mode.